Flip Chip/WLP Manufacturing and Market Analysis

Telecoms and Computing Market Report has been published today. It provides updated in 2018 year analysis of telecoms and computing industries.

Advanced wafer-level packaging technologies hold the key to meeting future technology needs, from mobile devices to automotive applications, to those required for enabling the IoT. Flip chip technology is slowly replacing wire bonding for many high-performance chips. Flip Chip (FC) is not a specific package (like SOIC), or even a package type (like BGA). Flip Chip describes the method of electrically connecting the die to the package carrier whereby the interconnection between the die and carrier is made through a conductive "bump" or copper pillar that is placed directly on the die surface. The bumped die is then "flipped over" and placed face down, with the bumps connecting to the carrier directly.

This technology can be applied on application processor, baseband, PMIC, memory devices, etc. products. For mobile communications, flip chip development is driven by increased device performance and package miniaturization trends, particularly for the CPU or so called applications processor that powers smart phones and media tablets.

To meet the needs of thinner mobile devices, Wafer Level Packages (WLPs) have been developed. They differ from flip-chip packages primarily in that the die is mounted directly on the PCB. The reduced form factor provided by mounting the die directly on the PCB has vaulted WLP to the leading position for smartphones and other products where space is at a premium. In Fan-in WLP chips, I/Os are generally fanned in across the die surface using RDL buildup layers to produce an area array, and solder bumps are formed at the terminals by ball drop or plating. But as die footprints shrink and I/Os increase, Fan-in WLP has run into limits on the number of I/Os it can support.

Fan-out WLP (FO-WLP) enables redistribution of I/Os beyond the chip footprint, differing from Fan-in WLP in several key areas. The FO-WLP process typically starts when individual dies are placed on double-sided tape sitting on a silicon carrier. The die is covered with a mold compound, and the carrier and tape are removed, leaving the die embedded in the mold. The wafer is turned over; an RDL is created, and solder balls are formed on top, just as in a Fan-in WLP. The extra panel surface area around the chip permits I/Os to be both fanned in over the chip and fanned out across the mold compound, making it possible to accommodate a larger number of I/Os.

One major advantage of FO-WLP, especially in mobile applications, is that the elimination of the substrate reduces the vertical footprint by an average of 40% compared with Fan-in WLP, enabling thinner products or making it possible to stack more components in the same form factor. The elimination of the interposer and TSVs also provides a cost reduction and eliminates concerns on the effects of TSVs on electrical behavior. The reduced path to the heat sink also helps improve thermal performance.

According to this report entitled “Flip Chip/WLP Manufacturing and Market Analysis,” the number of packages utilizing WLP will equal Flip Chip shipments in 2018 and then continue growing at a compound annual growth rate of 15% (between 2014 and 2020) compared to just 5% for Flip Chip, as shown in the graphic below.